Version Numbers

ArchC models follow a roadmap that assigns version numbers to certify models according to its stability level. A model has its version increased only if it reaches a well determined development stage defined in the roadmap.

PowerPC

PowerPC (PPC) is a RISC architecture. Its first release appeared in 1991, as a joint project of IBM, Motorola and Apple. PowerPC processors became famous for equipping Apple's Machintosh machines. Nowadays, PowerPC has a big family of processors both from IBM and Motorola, that are widely used both on desktop and embedded systems. Our PPC model implements the PowerPC 32 bits instruction set, including ABI simulation.

You can load applications compiled by your GCC PPC port. For additional information on how to load binary application files see the ArchC simulator page.

To simulate applications including I/O emulation, compile your model using the GCC PPC port available at the Compilers download page.

PowerPC Functional Model

Current Version:
Developers: Bruno Corsi
Proceed to the models download page.

MIPS-I

MIPS is a well known RISC architecture based on a five-stage pipeline datapath that contains an integer unit plus a 32-bit register bank and two special registers used for multiplication and division. These models implement a MIPS-I ISA description, including delay slots and ABI simulation. Pipeline simulation is included only in R3000 the cycle-accurate model.

You can load MIPS applications compiled by your GCC port, as long as you generate code using the MIPS-I instruction set. For additional information on how to load binary application files see the ArchC simulator page.

To simulate applications including I/O emulation, compile your model using the GCC MIPS port available at the Compilers download page.

MIPS-I Functional Model

Current Version: 0.7.6
Developers: Sandro Rigo and Marcus Bartholomeu
Proceed to the models download page.

SPARC-V8

SPARC is another well known RISC architecture, based on a five-stage pipeline. SPARC has specific features, like window registers, and a more complicated ISA if compared with the MIPS-I ISA. This model implements the V8 version of the SPARC architecture, including delay slots, window registers and ABI emulation.

You can load applications compiled by your GCC port for SPARC, using the -mv8 option if you want to use the whole V8 instruction set. For additional information on how to load binary application files see the ArchC simulator page.

To simulate applications including I/O emulation, compile your model using the GCC SPARC port available at the Compilers download page.

SPARC-V8 Functional Model

Current Version: 0.7.7
Developers: Marcus Bartholomeu (starting from an early version written by Pablo Viana and Cristiano Araujo).
Proceed to the models download page.

Intel 8051

The Intel 8051 microcontroller is one of the most used microcontroller family for embedded control. It is a CISC architecture, with a larger and more complicated ISA, if compared with a RISC machine, including multi-cycle instructions with variable length.

You can load applications stored in files respecting the ArchC loader hexadecimal format. For additional information on how to load hexadecimal application files see the ArchC simulator page.

The i8051 ArchC model has been donated by the GRECO group from CIn-UFPE.

i8051 Functional Model

Current Version: 0.3.3
Developers: Tiago Sampaio Lins
Proceed to the models download page.

PIC 16F84

The Microchip PIC 16F84 micro-controller is a well-known RISC CPU. It has 35 single-word instructions, which execute within a single cycle, except for branches, which execute in two cycles.
PIC 16F84 has an eight-level deep stack and separate instructions and data buses (Harvard architecture) with 14 and 8 bits, respectively.

The model can execute binary code applications targeted to its instruction-set architecture. For additional information on how to load hexadecimal application files see the ArchC simulator page.

The PIC 16F84 ArchC model has been donated by the Systems Design Automation Lab group from UFSC.

PIC 16F84 Functional Model

Current Version: 0.3.0
Developers: Leonardo Taglietti e Gabriel Renaldo Laureano
Proceed to the models download page.